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Quantum-Resilient Foundations for Next-Generation SoCs

AegisPQC™ Silicon IP Cores

As the 2030 NIST "Compliance Cliff" approaches, the demand for integrated, crypto-agile security has moved from a "feature" to a "requirement." The AegisPQC™ IP Series provides semiconductor architects with a drop-in, silicon-proven portfolio of accelerators designed to handle the mandatory NIST FIPS 203, 204, and 205 standards, as well as the 2026 "on-ramp" backups like HQC and Falcon.

The Aegis Advantage: Beyond the Lattice

While most IP providers offer fixed-function lattice accelerators, AegisPQC™ features our proprietary Agile-Poly™ Engine. This dedicated polynomial function accelerator ensures your SoC remains secure even if the industry shifts toward code-based or multivariate signatures.

Core Portfolio
1. AegisPQC-Lite IP (Ultra-Low Power)
  • Target: IoT, Wearables, Medical Devices, and Automotive Sensors.

  • Key Feature: Zero-wait-state ML-KEM encapsulation at sub-milliwatt power.

  • Performance: < 100k gates; optimized for ARM® Cortex-M and RISC-V extensions.

2. AegisPQC-Pro IP (High-Performance)
  • Target: Cloud Servers, 5G Base Stations, and VPN Concentrators.

  • Key Feature: Parallelized NTT (Number Theoretic Transform) engines supporting up to 20,000 ops/s.

  • Scalability: Multi-core clustering support for multi-terabit traffic decryption.

3. AegisPQC-Poly™ Accelerator (The "Ace" Core)
  • Target: Mission-critical infrastructure and long-lifecycle systems.

  • Key Feature: Universal Polynomial Arithmetic. Accelerates binary field multiplication for HQC and BIKE, and floating-point FFTs for Falcon (FN-DSA).

  • Agility: Hardware-level support for GF(2)[x] and GF(p)[x].

Why License AegisPQC IP?
  • Silicon-Proven Sovereignty: Our cores are designed and verified for the most stringent "Root of Trust" requirements, ensuring no backdoors and full FIPS 140-3 Level 3 readiness.

  • Unified Software Stack: Every IP core license includes our Aegis-Link SDK, providing pre-written OpenSSL providers and PKCS#11 drivers that talk directly to the hardware.

  • The 512-Point Advantage: Unlike competitors locked into 256-point NTTs, our Pro core natively handles the 512-point transforms required for Falcon and advanced lattice research.

Licensing & Delivery

We offer flexible licensing models tailored to your volume and integration needs:

  1. RTL Source Code: Verilog/SystemVerilog for full integration.

  2. Hard Macro: GDSII optimized for TSMC, Samsung, and Intel Foundry nodes.

  3. FPGA Bitstream: For rapid prototyping and pre-silicon validation.

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